1. Field of the Invention
The present invention relates to a sampling circuit, particularly to a sampling circuit and a master-slave flip-flop, which can control the sampling timing.
2. Description of the Prior Art
How to correctly sample signals is a critical problem for circuit design. However, many factors, such as PVT (Process-Voltage-Temperature) variation, low supply voltage, and overclocking, may cause timing errors and thus result in sampling errors. The conventional technology uses a signal transition detector to detect timing errors. While an error occurs, the value sampled at the corresponding timing is abandoned directly, and the signal is resampled in the next cycle. Alternatively, the time interval for sampling elongated whenever a timing error occurs. Thus, a cycle of time is wasted. The signal transition detector compares the output value of the logic circuit with the output value after a delay to determine whether an error occurs. However, the output value after a delay, which may be a correct result of the shortest path of the logic circuit, is likely to be misjudged as a result of a timing error. Hence, the time of a shortest path in a logic circuit must be strictly limited, which lead to expansion of logic circuit area, least signal competition lead to misjudgment of time errors.
Therefore, it is highly desirable to develop a sampling circuit with timing error tolerance.